iverilog compiling — hello world

iverilog compiling — hello world


This video shows how to use iverilog
to compile a verilog program and generate an executable. The process is
similar to compiling a C or C++ program. I’ll start with a simple hello world
program. So we first create the source hello.v. v here represents verilog and this module will print out
the message hello world. So we start with the module called hello_world and to start with initial begin and we use the display function to display
the message hello world and delay for 80 time units before
finish so we compile this like how we compile a C++ program .. … default output is a.out …. -… … ..
we can create a Makefile so in this Makefile we specify the default program .. the compiler is iverilog the
source code is hello.v and the output ….. tab okay so this is our simple makefile
so we can make again the hello is generated so you get
the same print out. Now we can also link two programs together.
Suppose we create another module sum. Suppose we call it sum.v
which adds two numbers so we say ….. variable and we specify that it is 16
bits bit15 to bit 0 a another input 15..0 b and output also 15 bit .. adds semicolon
and …. …. We can compile this as before… There’s no output…
now we can link this together with the the hello world to get something to get
an output value we modify our hello file and we need to need to insert some code … register …… … output is wire s and call the module sum, it is like
instantiation so we create an instance of sum, …. port… .. pin the port to a certain variable and then what we need to do is to start
with some value ..for example and now we can display the
values using function monitor .. …. now if we compile this you have an errorr ….. it says that it cannot find sum because
sum is in another file, sum.v. So we have to link them together. … … second is sum of 89 and 64 is 153
…. don’t want the output to be a.out you
can specify it so again you can put this in the Makefile
so we just … ………….. so I get the same result so this is a
very simple demonstration of compiling a Verilog program using iverilog. I’ll explain
more in the future. Thank you, bye bye.

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